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| 7 A H-Bridge for DC-Motor Applications TLE 7209-2R Preliminary Datasheet 1 1.1 Overview Features * Operating supply voltage 5 V to 28 V * Typical RDSon = 150 m for each output transistor (at 25 C) * Continuous DC load current 3.5 A (TC < 100 C) * Output current limitation at typ. 6.6 A 1.1 A * Short circuit shut-down for output currents over 8 A * Logic- inputs TTL/CMOS-compatible * Output switching frequency up to 30 kHz * Rise and fall times optimized for 0.5-2 kHz * Over-temperature protection * Short circuit protection * Undervoltage disable function * Diagnostic by SPI or Status-Flag (configurable) * Enable and Disable input * P-DSO-20-12 power package Type TLE 7209-2R Functional Description The TLE 7209-2R is an intelligent full H-Bridge, designed for the control of DC and stepper motors in safety critical applications and under extreme environmental conditions. The H-Bridge is protected against over-temperature and short circuits and has an under voltage lockout for all the supply voltages "VS" (main DC power supply). All malfunctions cause the output stages to go tristate. The device is configurable by the DMS pin. When grounded, the device gives diagnostic information via a simple error flag. When supplied with VCC = 5 V, the device works in SPI mode. In this mode, detailed failure diagnosis is available via the serial interface. Ordering Code on request Package P-DSO-20-12 Preliminary Datasheet 1 V1.0, 2004-mar-12 TLE 7209-2R Overview 1.2 Pin Configuration GND S C K /S F IN 1 VS CP VS O UT1 O UT1 SDO SDI GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 GND IN 2 D IS CSN VS O U T2 O U T2 EN DMS GND M etal slug is connected to G N D pins internally Figure 1 Table 1 Pin. No. 1 2 3 4 5, 16 6, 7 8 9 10 11 Pinout TLE 7209-2R Pin Definitions and Functions Symbol GND SCK/SF IN1 Function Ground SPI-Clock/Status-flag Input 1 Supply voltage for internal charge pump Supply voltage; connect pins externally Output 1; connect pins externally Serial data out Serial data in Ground Ground VSCP VS OUT1 SDO SDI GND GND Preliminary Datasheet 2 V1.0, 2004-mar-12 TLE 7209-2R Overview Table 1 Pin. No. 12 13 14, 15 17 18 19 20 Pin Definitions and Functions (cont'd) Symbol DMS EN OUT2 CSN DIS IN2 GND Function Diagnostic-Mode selection (+ Supply voltage for SPI-Interface) Enable Output 2; connect pins externally Chip Select (low active) Disable Input 2 Ground Preliminary Datasheet 3 V1.0, 2004-mar-12 TLE 7209-2R Overview 1.3 Block Diagram DMS VSCP VS Bias Charge Pump FaultDetect EN DIS CSN SDI SDO SCK/SF SPI 8 Bit Logic and Latch Driver OUT 1 & GateControl OUT 2 IN1 IN2 Direct Input Under Voltage Over Temperature GND Figure 2 Block Diagram TLE 7209-2R Preliminary Datasheet 4 V1.0, 2004-mar-12 TLE 7209-2R Circuit Description 2 2.1 Circuit Description Control Inputs The bridge is controlled by the Inputs IN1, IN2, DIS and EN as shown in Table 2. The outputs OUT1 and OUT2 are set to High or Low by the parallel inputs IN1 and IN2, respectively. In addition, the outputs can be disabled (set to tristate) by the Disable and Enable inputs DIS and EN. Inputs IN1, IN2 and DIS have an internal pull-up. Input EN has an internal pull-down. Table 2 Pos. 1. Forward 2. Reverse 3. Free-wheeling low 4. Free-wheeling high 5. Disable 6. Enable 7. IN1 disconnected 8. IN2 disconnected 9. DIS disconnected 10. EN disconnected 11. Current limit. active 12. Under Voltage 13. Over-temperature 14. Over-current 1) 2) Functional Truth Table DIS EN L L L L H X L L Z X L X X X H H H H X L H H X Z H X X X IN1 IN2 OUT1 H L L H X X Z X X X X X X X L H L H X X X Z X X X X X X H L L H Z Z H X Z Z Z Z Z Z OUT2 SF1) SPI2) DIA_REG L H L H Z Z X H Z Z Z Z Z Z H H H H L L H H L L H L L L see Chapter 2.4.2 If Mode "Status-Flag" is selected (see Chapter 2.4) If Mode "SPI-Diagnosis" is selected (see Chapter 2.4) Preliminary Datasheet 5 V1.0, 2004-mar-12 TLE 7209-2R Circuit Description 2.2 Power Stages Four n-channel power-DMOS transistors build up the output H-bridge. Integrated circuits protect the outputs against over current and over-temperature if there is a short-circuit to ground, to the supply voltage or across the load. Positive and negative voltage spikes, which occur when switching inductive loads, are limited by integrated freewheeling diodes. To drive the gates of the high-side DMOS, an internal charge pump is integrated to generate a voltage higher than the supply voltage. 2.2.1 Chopper Current Limitation To limit the output current at low power loss, a chopper current limitation is integrated as shown in Figure 3. The current is measured by sense cells integrated in the low-side switches. As soon the current limit IL is reached, all switches are switched off for a fixed time ta. current limit IL IOUT off-time t a time Figure 3 Chopper current limitation Preliminary Datasheet 6 V1.0, 2004-mar-12 TLE 7209-2R Circuit Description 2.2.2 Temperature-depending Current Reduction For 165 C < Tj < 175 C the current limit decreases from IL = 6.6 A 1.1 A to IL = 2.5 A 1.1 A as shown in Figure 4 A 6.6A IL tolerance of temperature dependent current reduction range of overtemperature shutdown 2.5A Tj 165C 175C C Figure 4 Temperature dependent current reduction 2.3 Protection The TLE 7209-2R is protected against short circuits, overload and invalid supply voltage by the following measures: 2.3.1 Short circuit to Ground The high-side switches are protected against a short of the output to ground by an over current shut-down. If a high-side switch is turned on and the current rises above the short circuit detection current IOUK all output transistors are turned off after a typical filter time of 2 s, and the error bit "Short Circuit to Ground on output 1 (2)", SCG1 (SCG2) is stored in the internal status register. 2.3.2 Short circuit to VS Due to the chopper current regulation, the low-side switches are already protected against a short to the supply voltage. To be able to distinguish a short circuit from normal current limit operation, the current limitation is deactivated for the blanking time tb after the current has exceeded the current limit threshold IL. If the short circuit detection current IOUK is reached within this blanking time, a short circuit is detected (see Figure 5). All output transistors are turned OFF and the according error bit "Short Circuit to Battery on output 1 (2)", SCB1 (SCB2) is set. Preliminary Datasheet 7 V1.0, 2004-mar-12 TLE 7209-2R Circuit Description IN IN IOUK tb IL IOUT IOUT ta tb tb IOUK IL time time Figure 5 Short to Vs detection. Left: normal operation. Right: short circuit is detected 2.3.3 Short circuit across the load If short circuit messages from high- and low-side switch occur simultaneously within a delay time of typically 2s, the error bit "Short Circuit Over Load", SCOL is set. 2.3.4 Over-Temperature In case of high DC-currents, insufficient cooling or high ambient temperature, the chip temperature may rise above the thermal shut-down temperature TSD. In that case, all output transistors are shut-down and the error-bit "Over-Temperature", OT is set. 2.3.5 Under-Voltage shut-down If the supply-voltage at the VS pins falls below the under-voltage detection threshold, the outputs are set to tristate and the error-bit "Under-Voltage at VS" is set. 2.4 Diagnosis The Diagnosis-Mode can be selected between SPI-Diagnosis and Status-Flag Diagnosis. The choice of the Diagnosis-Mode is selected by the voltage-level on Pin 12 (DMS Diagnosis Mode Selection): * DMS = GND, Status-Flag Mode * DMS = VCC, SPI-Diagnosis Mode For the connection of Pins SDI, SDO, CSN and SCK/SF see Figure 14 and Figure 15. Preliminary Datasheet 8 V1.0, 2004-mar-12 TLE 7209-2R Circuit Description 2.4.1 2.4.1.1 Status-Flag (SF) Mode (DMS = GND) SF output In SF-mode, pin 2 is used as an open-drain output status-flag. The pin has to be pulled to the logic supply voltage with a pull-up resistor, 47 kOhm recommended. In case of any failure that leads to a shut-down of the outputs, the status-flag is set (e.g. SF pin pulled to low). These failures are: - - - - - Under Voltage on VS Short circuit of OUT1 or OUT2 against VS or GND Short circuit between OUT1 and OUT2 Over-current Over-temperature SF is also pulled low when the outputs are disabled by EN or DIS. 2.4.1.2 Fault storage and reset - In case of under-Voltage, the failure is not latched. As soon as VS falls below the under-Voltage detection threshold, the output stage switches in tristate and the statusflag is set from high level to low-level. If the voltage has risen above the specified value again, the output stage switches on again and the status-flag is reset to high-level. The Under Voltage failure is shown at the SF pin for VS in the voltage range below the detection threshold (typical 4.2V) down to 2.5V. - In the SF-mode, all internal circuitry is supplied by the voltage on VS. For that reason, a loss of VS supply voltage leads to a reset of all stored information (Power-ONReset). This Power-ON-Reset occurs as soon as under-Voltage is detected on VS - In case of short circuit, over-current or over-temperature, the fault will be stored. The output stage remains in tristate and the status-flag at low-level until the error is reset by one of the following conditions: H -> L on DIS, L -> H on EN or Power-ON Reset. 2.4.2 2.4.2.1 SPI-Mode (DMS = 5V) SPI-Interface The serial SPI interface establishes a communication link between TLE 7209-2R and the systems microcontroller. The TLE 7209-2R always operates in slave mode whereas the controller provides the master function. The maximum baud rate is 2 MBaud (200pF on SDO). By applying an active slave select signal at CSN the TLE 7209-2R is selected by the SPI master. SDI is the data input (Slave In), SDO the data output (Slave Out). Via SCK (Serial Clock Input) the SPI clock is provided by the master. In case of inactive slave select signal (High) the data output SDO goes into tristate. Preliminary Datasheet 9 V1.0, 2004-mar-12 TLE 7209-2R Circuit Description The first two bits of an instruction may be used to establish an extended deviceaddressing. This gives the opportunity to operate up to 4 Slave-devices sharing one common CSN signal from the Master-Unit (see Figure 7) DMS S P I p o w e rs u p p ly CSN SCK S P I - C o n t r o l: - > s t a t e m a c h in e - > c lo c k c o u n t e r - > in s t r u c t io n r e c o g n i t io n s h if t - r e g i s t e r 8 SDI SDO D IA _ R E G R eset 8 D ia g n o s t ic s DMS U n d e rv o lt a g e D IS OR EN Figure 6 2.4.2.2 SPI block-diagram Characteristics of the SPI Interface 1. When DMS is > 3.5V, the SPI is active, independently of the state of EN or DIS. During active reset conditions (DMS < 3.5V) the SPI is driven into its default state. When reset becomes inactive, the state machine enters into a wait-state for the next instruction. 2. If the slave select signal at CSN is inactive (high), the state machine is forced to enter the wait-state, i.e. the state machine waits for the following instruction. 3. During active (low) state of the select signal CSN the falling edge of the serial clock signal SCK will be used to latch the input data at SDI. Output data at SDO are driven with the rising edge of SCK (see timing diagram Figure 13) 4. Chip-address: In order to establish the option of extended addressing the uppermost two bits of the instruction-byte (i.e the first two SDI-bits of a Frame) are reserved to send a chipaddress. To avoid a bus conflict the output SDO must stay high impedance during the addressing phase of a frame (i.e. until the address-bits are recognized as valid chipaddress). If the chip-address does not match, the data at SDI will be ignored and SDO remains high impedance for the complete frame. See also Figure 7 5. Verification byte: Simultaneously to the receipt of an SPI instruction TLE 7209-2R transmits a verification byte via the output SDO to the controller. Refer to Figure 8. This byte indicates normal or abnormal operation of the SPI. It contains an initial bit pattern and a flag indicating an error occurred during the previous access. Preliminary Datasheet 10 V1.0, 2004-mar-12 TLE 7209-2R Circuit Description 6. Because only read access is used in the TLE 7209-2R, the SDI data-bits (2nd byte) are not used 7. Invalid instruction/access: An instruction is invalid if an unused instruction code is detected (see tables with SPI instructions). In case an unused instruction code occurred, the data byte "ffhex" (no error) will be transmitted after having sent the verification byte. This transmission takes place within the same SPI-frame that contained the unused instruction byte. In addition any transmission is invalid if the number of SPI clock pulses (falling edge) counted during active CSN differs from exactly 16 clock pulses. If an invalid instruction is detected, bit TRANS_F in the following verification byte (next SPI transmission) is set to HIGH. The TRANS_F bit must not be cleared before it has been sent to the micro controller. 8. Transfer error bit TRANS_F: The bit TRANS_F indicates an error during the previous transfer. An error is considered to have occurred when an invalid command was sent, the number of SPI clock pulses (falling edge) counted during active CSN was less than or greater than 16 clock pulses, or SPI clock (SCK) was logical high during falling edge of CSN. Preliminary Datasheet 11 V1.0, 2004-mar-12 TLE 7209-2R Circuit Description SDO remains tristated after CSN active Address sent by master is "00" Correct addres is recognized, data transmitted to SDO CSN SCK SDI SDO Z 7 7 6 6 5 5 5 4 4 4 3 3 3 2 2 2 1 1 1 0 0 0 7 7 7 6 6 6 5 5 5 4 4 4 3 3 3 2 2 2 1 1 1 0 0 0 SDO remains tristated after CSN active Address sent by master is differnt from "00" Correct addres is not recognized, SDO remains tristated and SDI data are ignored CSN SCK SDI SDO 7 7 6 5 5 4 4 3 3 2 1 1 Z 0 0 7 6 6 5 5 4 3 3 2 2 1 1 0 0 6 2 7 4 Figure 7 Bus-arbitration by chip-address Preliminary Datasheet 12 V1.0, 2004-mar-12 TLE 7209-2R Circuit Description 2.4.2.3 SPI-Communication The 16 input bits consist of the SPI-instruction byte and a second, unused byte. The 16 output bits consist of the verification-byte and the data-byte (see also Figure 8). The definition of these bytes is given in the subsequent sections. CSN SCK SDI SDO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 MSB MSB SPI Instruction Verification byte LSB LSB MSB not used data-byte LSB Figure 8 2.4.2.4 SPI communication SPI instruction The uppermost 2 bit of the instruction byte contain the chip-address. The chip-address of the TLE 7209-2R is 00. During read-access, the output data according to the register requested in the instruction byte are applied to SDO within the same SPI frame. That means, the output data corresponding to an instruction byte sent during one SPI frame are transmitted to SDO during the same SPI frame. Table 3 MSB 7 0 Table 4 Bit 7,6 5-1 0 6 0 Name CPAD1,0 INSTR (4-0) INSW 5 INSTR4 4 INSTR3 3 INSTR2 2 INSTR1 1 INSTR0 0 INSW SPI Instruction Format SPI instruction Description Description Chip Address (has to be `0', `0') SPI instruction (encoding) Even parity Preliminary Datasheet 13 V1.0, 2004-mar-12 TLE 7209-2R Circuit Description Table 5 SPI Instruction-Bytes Encoding Encoding bit 7,6 bit 5-1 CPAD1,0 INSTR(4-0) RD_IDENT RD_VERSION RD_DIA - - SPI Instruction Description Bit 0 INSW 0 1 1 x x read identifier read version read DIA_REG unused, TRANS_F is set to high, ff_hex is sent as data bit invalid address, SDO remains tristate during entire SPI frame 00 00 00 00 all others 00000 00001 00100 all others xxxxx 2.4.2.5 Table 6 MSB 7 Z Verification Byte Verification Byte Format 6 Z 5 1 4 0 3 1 2 0 1 1 0 TRANS_F Table 7 Bit 0 1 2 3 4 5 6 7 Verification Byte Description Name TRANS_F Description Bit = 1: error detected during previous transfer Bit = 0: previous transfer was recognized as valid Fixed to High Fixed to Low Fixed to High Fixed to Low Fixed to High send as high impedance send as high impedance The default value after power-up at DMS of the TRANS_F bit is L (previous transfer valid) Preliminary Datasheet 14 V1.0, 2004-mar-12 TLE 7209-2R Circuit Description 2.4.2.6 ) Data-byte: Diagnostics/Encoding of Failures (Register DIA_REG, SPI Instruction RD_DIA) DIA_REG Format 6 OT 5 CurrRed 4 CurrLim 3 DIA21 2 DIA20 1 DIA11 0 DIA10 Table 8 MSB 7 EN/DIS Table 9 Bit 0 1 2 3 4 5 6 7 DIA_REG Description Name DIA 10 DIA 11 DIA 20 DIA 21 CurrLim Description Diagnosis-Bit1 of OUT1 Diagnosis-Bit2 of OUT1 Diagnosis-Bit1 of OUT2 Diagnosis-Bit2 of OUT2 is set to 0" in case of current limitation. latch behavior see below see below see below see below latched latched latched not latched Default value after reset is FFhex. Access by controller is read only CurrRed is set to 0" in case of temperature dependent current limitation OT EN/DIS is set to 0" in case of over-temperature is set to 0" in case of EN = L or DIS = H EN H L H L DIS L L H H DIA_REG_7 1 0 0 0 Preliminary Datasheet 15 V1.0, 2004-mar-12 TLE 7209-2R Circuit Description Table 10 Encoding of the Diagnostic Bits of OUT1 and OUT2 latch behavior latched DIA21 DIA20 DIA11 DIA10 Description 1 0 0 1 1 0 1 0 1 0 1 0 0 0 1 1 1 0 0 1 0 1 1 0 Short circuit over load (SCOL) Short circuit to battery on OUT1 (SCB1) latched Short circuit to ground on OUT1 (SCG1) latched No error detected on OUT1 Open load (OL) latched Short circuit to battery on OUT2 (SCB2) latched Short circuit to ground on OUT2 (SCG2) latched No error detected on OUT2 Under Voltage on Pin Vs not latched Failure Encoding in case of multiple faults If multiple faults are stored in the failure register, the faults that are encoded in the DIAxx bits can not be displayed simultaneously due to the encoding scheme that is used. In this case, errors are encoded according to the following priority list. - Priority 1: Under Voltage (please note that after removal of Under Voltage, the original error will be restored, see below) - Priority 2: Short circuit across the load - Priority 3: all other short circuits - Priority 4: open load If a failure of higher priority is detected, the failures of lower priority are no longer visible in the encoded SPI message. Fault storage and reset of the Diagnosis Register DIA_REG Register DIA_REG is reset upon the following conditions: - With the rising edge of the CSN-Signal after the SPI-instruction RD_DIA. This reset only takes place if the correct number of 16 SCK pulses has been counted. - When the voltage on DMS exceeds the threshold for detecting SPI-Mode (after Under Voltage condition). Under Voltage on Vs (typ. < 5,0V) sets Bit 0.... Bit 3 of DIA_REG to 0000. If Vs rises above the Under Voltage level, Bits of DIA_REG are restored (when DMS > 3.5V). - A rising edge on EN or a falling edge on DIS re-activates the output power-stages, and resets the DIA_REG register. Preliminary Datasheet 16 V1.0, 2004-mar-12 TLE 7209-2R Circuit Description 2.4.2.7 Data-byte: Device Identifier and Version (SPI instructions RD_IDENT and RD_VERSION) The IC`s identifier (device ID) and version number are used for production test purposes and features plug & play functionality depending on the systems software release. The two numbers are read-only accessible via the SPI instructions RD_IDENT and RD_VERSION as described in Section 2.4.2.4. The device ID is defined to allow identification of different IC-Types by software and is fixed for the TLE 7209-2R. The Version number may be utilized to distinguish different states of hardware and is updated with each redesign of the TLE 7209-2R. The contents is divided into an upper 4 bit field reserved to define revisions (SWR) corresponding to specific software releases and a lower 4 bit field utilized to identify the actual mask set revision (MSR). Both (SWR and MSR) will start with 0000b and are increased by 1 every time an according modification of the hardware is introduced. Reading the IC Identifier (SPI Instruction: RD_IDENT): Table 11 MSB 7 ID7 Table 12 Bit 7...0 6 ID6 5 ID5 4 ID4 3 ID3 2 ID2 1 ID1 0 ID0 Device Identifier Format Device Identifier Description Name device-ID(7...0) Description ID-No.: 10100010 Reading the IC version number (SPI Instruction: RD_VERSION): Table 13 MSB 7 SWR3 Table 14 Bit 7...4 3...0 6 SWR2 5 SWR1 4 SWR0 3 MSR3 2 MSR2 1 MSR1 0 MSR0 IC version number Format IC version number Description Name SWR(3...0) MSR(3...0) Description This register is set to 0 Version corresponding to Mask set Preliminary Datasheet 17 V1.0, 2004-mar-12 TLE 7209-2R Circuit Description 2.4.2.8 Open-Load Diagnosis Open-load diagnostic in OFF-state is only possible in the SPI-mode (DMS = 5 V) if the device is Disabled (EN = L or DIS = H). The detection mechanism is depicted in Figure 9. The according diagnostic information can be read out via the SPI diagnostic register. The resulting overall diagnostic truth-table is shown as Table 15 VS DMS VS 1.5mA + DIS OR EN AND OUT1 OUT2 1V + 1V 1mA 1 to diagnostic register AND Figure 9 Table 15 Functional block diagram of open-load detection Diagnosis Truth Table for open load detection Output stage inactive, EN = low or DIS = high, DMS > 4.5 V OUT1 OUT2 Load available Open Load H H H L L L L H OL detected OL not detected - double Fault OL detected OL detected OL not detected - double Fault SC -> GND on OUT1 and Open Load L SC -> GND on OUT2 and Open Load H SC -> VS on OUT1 and Open Load SC -> VS on OUT2 and Open Load H H Preliminary Datasheet 18 V1.0, 2004-mar-12 TLE 7209-2R Electrical Characteristics 3 3.1 Pos. 3.1.1 3.1.2 3.1.3 3.1.4 Electrical Characteristics Absolute Maximum Ratings Parameter Sym- Limit Values Unit Test Conditions bol min. max. -40 - Storage temperature Ts Ambient temperature Ta Supply voltage -55 -40 -1 -2 +150 +175 +125 +125 40 40 C C C C V V - dynamic: t < 1 s - - static destruction proof dynamic destruction proof t < 0.5 s (single pulse, Tj < 85 C) In status-flag-mode, SF pull-up R 10 k Junction temperature Tj VS 3.1.5 Voltage at logic inputs IN1, IN2, DIS, EN, SDI, SCK/SF V -0.5 18 V 3.1.6 3.1.7 Voltage at logic input V CSN Voltage at logic input V DMS and logic output SDO Voltage at VsCP -0.5 -0.5 40 13 V V - 3.1.8 3.1.9 VCP VS 0.5 VS + 0.5 - - V - ESD voltage human 3.1.10 body model (MIL STD 883D / ANSI EOS\ESD S5.1) VESD - VESD-- - OUT 4kV all pins 8kV only pins 6, 7, 14 and 15 (outputs) Note: Maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit. Preliminary Datasheet 19 V1.0, 2004-mar-12 TLE 7209-2R Electrical Characteristics 3.2 Pos. 3.2.1 3.2.2 3.2.3 Operating Range Parameter Supply Voltage DMS Supply Voltage PWM frequency Symbol VS VDMS f Limit Values min. 5 3.5 - max. 28 5.5 30 V V kHz Device in SPI-mode May be limited to lower values in the application due to switching losses Unit Remark 3.2.4 Junction Temperature TJ -40 150 C Note: In the operating range, the circuit functionality as described in the circuit description is fulfilled. 3.3 3.3.1 3.3.2 Thermal Resistance Junction-case Junction-ambient RthJC RthJA - - 1.5 50 K/W K/W specified by design minimal footprint 3.4 Pos. Electrical Characteristics Parameter Symbol Limit Values min. typ. max. Unit Test Conditions 5V < VS < 28V; - 40 C < Tj < 150 C; unless otherwise specified Power Supply 3.4.1 Under voltage at VS VUV OFF VUV ON VUV HY 3.4.2 Supply current 3.4 3.6 100 - - - - 4.2 4.4 5 5.2 1000 30 20 mV mA mA V Switch off threshold Switch on threshold Hysteresis IUB f = 20 kHz, IOUT = 0 A f = 0 Hz, IOUT = 0 A Preliminary Datasheet 20 V1.0, 2004-mar-12 TLE 7209-2R Electrical Characteristics 3.4 Pos. Electrical Characteristics (cont'd) Parameter Symbol Limit Values min. typ. max. Unit Test Conditions 5V < VS < 28V; - 40 C < Tj < 150 C; unless otherwise specified Logic Inputs IN1, IN2, DIS, EN 3.4.3 3.4.4 3.4.5 3.4.6 3.4.7 Input "high" Input "low" Input hysteresis pull-up current IN1, IN2, DIS pull-down current EN VIH VIL VIHY IIL IIH 2 - 0.1 -200 - - - - -125 - - 1 0.6 - 100 V V V A A - - - U1V U2V Power Outputs OUT1, OUT2 3.4.8 3.4.9 3.4.10 3.4.11 3.4.12 3.4.13 3.4.14 3.4.15 Switch on resistance Switch-off current Switch-off time Blanking time Switch-off Tracking Short circuit detection current Current Tracking Reactivation time after internal shut-down - - 5.5 - 8 8 1.0 8 2 - - 3.5 - 200 20 A A s - specified by design Over-current- or overtemperature shutdown to reactivation of the output stage Output stage switched off - 6.6 2.5 16 13 300 7.7 - 26 19 m A A s s ROUT-UB, ROUT-GND VS > 5 V -40 C < Tj < 165 C |IL| ta tb ta/tb Tj < 175 C Vs=13.2 V, L=2.2 mH, R=0.23 Vs=13.2 V, L=2.2 mH, R=0.23 |IOUK| |IOUK||IL| t Note: Reactivation time is not subject to production test; specified by design 3.4.16 3.4.17 Leakage current Free-wheel diode forward voltage - - - - - 200 2 A V UD IOUT = 3 A Preliminary Datasheet 21 V1.0, 2004-mar-12 TLE 7209-2R Electrical Characteristics 3.4 Pos. 3.4.18 Electrical Characteristics (cont'd) Parameter Free-wheel diode reverse recovery time Symbol Limit Values min. typ. - max. 100 ns Reverse recovery time is not subject to production test; specified by design - Unit Test Conditions 5V < VS < 28V; - 40 C < Tj < 150 C; unless otherwise specified trr Output Status-flag, Open Drain Output DMS < 0.8 V 3.4.19 3.4.20 Output "high" (SF not set) Output "low" (SF set) ISF ISF - 300 100 - - - 20 - - A A A VSF = 5 V VSF = 1 V VSF = 0.5 V Timing 3.4.21 Output ON-delay tdon - 6 s IN1 --> OUT1 resp. IN2 --> OUT2, IOUT = 3A IN1 --> OUT1 resp. IN2 --> OUT2, IOUT = 3A OUT1H --> OUT1L, OUT2H --> OUT2L, IOUT = 3 A OUT1L --> OUT1H, OUT2L --> OUT2H DIS --> OUTn, EN --> OUTn 3.4.22 Output OFF-delay tdoff - 6 s 3.4.23 Output switching time tr, tf - 5 s 3.4.24 3.4.25 3.4.26 3.4.27 Disable delay time Power on delay time Delay time for fault detection Minimum pulse width tddis - - - - - - 2 1.6 2 1 - 2.2 s ms s s VS = on --> output stage active - EN/DIS-->Reset DIA_REG tdf tden Preliminary Datasheet 22 V1.0, 2004-mar-12 TLE 7209-2R Electrical Characteristics 3.4 Pos. Electrical Characteristics (cont'd) Parameter Symbol Limit Values min. typ. max. Unit Test Conditions 5V < VS < 28V; - 40 C < Tj < 150 C; unless otherwise specified Input SCK, SPI Clock Input 3.4.28 3.4.29 3.4.30 3.4.31 3.4.32 Low Level High Level Hysteresis Input Capacity Input Current USCKL USCKH USCK - 2 0.1 - - - - - - 20 1 - 0.4 10 50 V V V pF A - - - - Pull-up current source connected to VCC CSCK -ISCK Input CSN, Chip Select Signal 3.4.33 3.4.34 3.4.35 3.4.36 3.4.37 Low Level High Level Hysteresis Input Capacity Input Current UCSNL UCSNH UCSN - 2 0.1 - - - - - - 20 1 - 0.4 10 50 V V V pF A TLE 7209-2R is selected - - - Pull up current source connected to VCC CCSN -ICSN Input SDI, SPI Data Input 3.4.38 3.4.39 3.4.40 3.4.41 3.4.42 Low Level High Level Hysteresis Input Capacity Input Current USDIL USDIH USDI - 2 0.1 - - - - - - 20 1 - 0.4 10 50 V V V pF A - - - - Pull up current source connected to VCC CSDI -ISDI Preliminary Datasheet 23 V1.0, 2004-mar-12 TLE 7209-2R Electrical Characteristics 3.4 Pos. Electrical Characteristics (cont'd) Parameter Symbol Limit Values min. typ. max. Unit Test Conditions 5V < VS < 28V; - 40 C < Tj < 150 C; unless otherwise specified Output SDO Tristate Output of the TLE 7209-2R (SPI output); 3.4.43 3.4.44 3.4.45 3.4.46 Low Level High Level Capacity Leakage Current VSDOL VSDOH CSDO ISDO - - 0.75 - -10 - 0.4 - 10 10 V V pF A ISDO = 2 mA ISDO = -2 mA Capacity of the pin in tristate In tristate VDMS - - - Note: All in- and output pin capacities are not subject to production test; specified by design Input DMS Supply-Input for the SPI-Interface and Selection Pin for SPI- or SF-Mode 3.4.47 3.4.48 Input Voltage Input Current VDMS VDMS IDMS 3.5 - - - - - - 0.8 10 V V mA SPI-Mode Status-Flag-Mode SPI-Mode Open-Load Diagnosis 3.4.49 Diagn. Threshold Load is available Load is missing 3.4.50 3.4.51 3.4.52 3.4.53 Pull-up Current Pull-down Current Tracking Diag. C Delay Time VOUT1 VOUT2 VOUT1 VOUT2 -IOUT1 0.8 0.8 1 - 1000 700 1.2 30 - - - - 1500 1000 1.5 - - - V V V V A A - ms DMS > 4.5 V, EN < 0.8 V or DIS > 4.5 V VS 0.8 2000 1400 1.7 100 IOUT2 - IOUT1/IOUT2 - tD Preliminary Datasheet 24 V1.0, 2004-mar-12 TLE 7209-2R Electrical Characteristics 3.4 Pos. Electrical Characteristics (cont'd) Parameter Symbol Limit Values min. typ. max. Unit Test Conditions 5V < VS < 28V; - 40 C < Tj < 150 C; unless otherwise specified SPI Timing (see Figure 13) 3.4.54 3.4.55 3.4.56 3.4.57 Cycle-Time (1) Enable Lead Time Enable Lag Time Data Valid tcyc (1) tlead (2) tlag (3) tv (4) 200 100 150 - - - - - - - - - - 40 150 ns ns ns ns ns referred to master referred to master referred to master CL = 40 pF CL = 200 pF referred to TLE 72092R 3.4.58 3.4.59 3.4.60 3.4.61 3.4.62 3.4.63 3.4.64 Data Setup Time Data Hold Time Disable Time Transfer Delay Select time Access time Clock inactive before chip select becomes valid Clock inactive after chip select becomes invalid tsu (5) th (6) tdis (7) tdt (8) tCSN (9) tacc (10) (11) 50 20 - 150 50 8.35 200 - - - - - - - - - 100 - - - - ns ns ns ns ns s ns referred to master referred to master referred to TLE 72092R referred to master referred to master referred to master - 3.4.65 (12) 200 - - ns - Temperature Thresholds 3.4.66 3.4.67 Start of current limit reduction Thermal Shut-down TILR TSD 150 175 - - - - C C Note: Temperature thresholds are not subject to production test; specified by design Preliminary Datasheet 25 V1.0, 2004-mar-12 TLE 7209-2R Timing Diagrams 4 Timing Diagrams V 5 INx 50% 0 50% 80% OUTx 20% tdon tdoff Figure 10 Output Delay Time V 5 DIS / EN 50% 0 OUTx 20% Z tddis Figure 11 Disable Delay Time Preliminary Datasheet 26 V1.0, 2004-mar-12 TLE 7209-2R Timing Diagrams tRISE tFALL 80% 80% OUTx 20% 20% Figure 12 Output Switching Time 10 9 CSN 11 2 1 3 8 SCK 12 4 7 SDO tristate Bit (n-3) Bit (n-4)...1 Bit 0; LSB 5 SDI 6 MSB IN Bit (n-2) Bit (n-3) Bit (n-4)...1 LSB IN n = 16 Figure 13 SPI-timing Preliminary Datasheet 27 V1.0, 2004-mar-12 TLE 7209-2R Application 5 Application VSCP DMS V-Reg Vcc IN1 IN2 DIS C CSN SDI SDO SCK/SF OUT 2 OUT 1 M VS from Watchdog or fail-safe Controller EN GND Figure 14 Application Example with SPI-Interface VSCP DMS V-Reg Vcc IN1 IN2 DIS C 47k CSN SDI SDO SCK/SF VS OUT 1 OUT 2 M from Watchdog or fail-safe Controller EN GND Figure 15 Application Example with Status-Flag 28 V1.0, 2004-mar-12 Preliminary Datasheet TLE 7209-2R Application Reverse polarity protection via main relay VS 100F 100nF TLE 7209-2R ignition switch battery Figure 16 Application Examples for Over-Voltage- and Reverse-Voltage Protection Preliminary Datasheet Vs < 40V main relay 29 V1.0, 2004-mar-12 TLE 7209-2R Package Outlines 6 Package Outlines P-DSO-20-12 (Plastic Dual Small Outline Package) 11 0.15 1) 3.5 MAX. 0 +0.1 3.25 0.1 B 0.25 +0.07 20 1 0.02 1.2 -0.3 2.8 1.27 15.74 0.1 (Heatslug) 0.25 M 1.3 6.3 (Mold) 14.2 0.3 11 0.1 A 20x Heatslug 0.95 0.15 0.25 B 0.4 +0.13 20 11 Index Marking Heatslug 1 x 45 1 10 10 13.7 -0.2 (Metal) 15.9 0.15 1) (Mold) 1) A 3.2 0.1 (Metal) 5.9 0.1 (Metal) 5 3 Does not include plastic or metal protrusion of 0.15 max. per side Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information" SMD = Surface Mounted Device Preliminary Datasheet 30 Dimensions in mm V1.0, 2004-mar-12 GPS05791 TLE 7209-2R Package Outlines TLE 7209-2R Revision History: Previous Version: Page 2004-mar-12 none V1.0 Subjects (major changes since last revision) Preliminary Datasheet 31 V1.0, 2004-mar-12 Edition 2004-mar-12 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 Munchen, Germany (c) Infineon Technologies AG 2004. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. 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